Noise Nugget SDK
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aic3105_reg_def.h
1#pragma once
2
3// Page select register
4#define AIC3X_PAGE_SELECT 0
5// Software reset register
6#define AIC3X_RESET 1
7// Codec Sample rate select register
8#define AIC3X_SAMPLE_RATE_SEL_REG 2
9// PLL progrramming register A
10#define AIC3X_PLL_PROGA_REG 3
11// PLL progrramming register B
12#define AIC3X_PLL_PROGB_REG 4
13// PLL progrramming register C
14#define AIC3X_PLL_PROGC_REG 5
15// PLL progrramming register D
16#define AIC3X_PLL_PROGD_REG 6
17// Codec datapath setup register
18#define AIC3X_CODEC_DATAPATH_REG 7
19// Audio serial data interface control register A
20#define AIC3X_ASD_INTF_CTRLA 8
21// Audio serial data interface control register B
22#define AIC3X_ASD_INTF_CTRLB 9
23// Audio serial data interface control register C
24#define AIC3X_ASD_INTF_CTRLC 10
25// Audio overflow status and PLL R value programming register
26#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
27// Audio codec digital filter control register
28#define AIC3X_CODEC_DFILT_CTRL 12
29// Headset/button press detection register
30#define AIC3X_HEADSET_DETECT_CTRL_A 13
31#define AIC3X_HEADSET_DETECT_CTRL_B 14
32// ADC PGA Gain control registers
33#define LADC_VOL 15
34#define RADC_VOL 16
35// MIC3 control registers
36#define MIC3LR_2_LADC_CTRL 17
37#define MIC3LR_2_RADC_CTRL 18
38// Line1 Input control registers
39#define LINE1L_2_LADC_CTRL 19
40#define LINE1R_2_LADC_CTRL 21
41#define LINE1R_2_RADC_CTRL 22
42#define LINE1L_2_RADC_CTRL 24
43// Line2 Input control registers
44#define LINE2L_2_LADC_CTRL 20
45#define LINE2R_2_RADC_CTRL 23
46// MICBIAS Control Register
47#define MICBIAS_CTRL 25
48
49// AGC Control Registers A, B, C
50#define LAGC_CTRL_A 26
51#define LAGC_CTRL_B 27
52#define LAGC_CTRL_C 28
53#define RAGC_CTRL_A 29
54#define RAGC_CTRL_B 30
55#define RAGC_CTRL_C 31
56
57// DAC Power and Left High Power Output control registers
58#define DAC_PWR 37
59#define HPLCOM_CFG 37
60// Right High Power Output control registers
61#define HPRCOM_CFG 38
62// High Power Output Stage Control Register
63#define HPOUT_SC 40
64// DAC Output Switching control registers
65#define DAC_LINE_MUX 41
66// High Power Output Driver Pop Reduction registers
67#define HPOUT_POP_REDUCTION 42
68// DAC Digital control registers
69#define LDAC_VOL 43
70#define RDAC_VOL 44
71// Left High Power Output control registers
72#define LINE2L_2_HPLOUT_VOL 45
73#define PGAL_2_HPLOUT_VOL 46
74#define DACL1_2_HPLOUT_VOL 47
75#define LINE2R_2_HPLOUT_VOL 48
76#define PGAR_2_HPLOUT_VOL 49
77#define DACR1_2_HPLOUT_VOL 50
78#define HPLOUT_CTRL 51
79// Left High Power COM control registers
80#define LINE2L_2_HPLCOM_VOL 52
81#define PGAL_2_HPLCOM_VOL 53
82#define DACL1_2_HPLCOM_VOL 54
83#define LINE2R_2_HPLCOM_VOL 55
84#define PGAR_2_HPLCOM_VOL 56
85#define DACR1_2_HPLCOM_VOL 57
86#define HPLCOM_CTRL 58
87// Right High Power Output control registers
88#define LINE2L_2_HPROUT_VOL 59
89#define PGAL_2_HPROUT_VOL 60
90#define DACL1_2_HPROUT_VOL 61
91#define LINE2R_2_HPROUT_VOL 62
92#define PGAR_2_HPROUT_VOL 63
93#define DACR1_2_HPROUT_VOL 64
94#define HPROUT_CTRL 65
95// Right High Power COM control registers
96#define LINE2L_2_HPRCOM_VOL 66
97#define PGAL_2_HPRCOM_VOL 67
98#define DACL1_2_HPRCOM_VOL 68
99#define LINE2R_2_HPRCOM_VOL 69
100#define PGAR_2_HPRCOM_VOL 70
101#define DACR1_2_HPRCOM_VOL 71
102#define HPRCOM_CTRL 72
103// Mono Line Output Plus/Minus control registers
104#define LINE2L_2_MONOLOPM_VOL 73
105#define PGAL_2_MONOLOPM_VOL 74
106#define DACL1_2_MONOLOPM_VOL 75
107#define LINE2R_2_MONOLOPM_VOL 76
108#define PGAR_2_MONOLOPM_VOL 77
109#define DACR1_2_MONOLOPM_VOL 78
110#define MONOLOPM_CTRL 79
111// Left Line Output Plus/Minus control registers
112#define LINE2L_2_LLOPM_VOL 80
113#define PGAL_2_LLOPM_VOL 81
114#define DACL1_2_LLOPM_VOL 82
115#define LINE2R_2_LLOPM_VOL 83
116#define PGAR_2_LLOPM_VOL 84
117#define DACR1_2_LLOPM_VOL 85
118#define LLOPM_CTRL 86
119// Right Line Output Plus/Minus control registers
120#define LINE2L_2_RLOPM_VOL 87
121#define PGAL_2_RLOPM_VOL 88
122#define DACL1_2_RLOPM_VOL 89
123#define LINE2R_2_RLOPM_VOL 90
124#define PGAR_2_RLOPM_VOL 91
125#define DACR1_2_RLOPM_VOL 92
126#define RLOPM_CTRL 93
127
128#define MODULE_POWER_STATUS 94
129
130// GPIO/IRQ registers
131#define AIC3X_STICKY_IRQ_FLAGS_REG 96
132#define AIC3X_RT_IRQ_FLAGS_REG 97
133
134#define AIC3X_CLOCK_REG 101
135// Clock generation control register
136#define AIC3X_CLKGEN_CTRL_REG 102
137// New AGC registers
138#define LAGCN_ATTACK 103
139#define LAGCN_DECAY 104
140#define RAGCN_ATTACK 105
141#define RAGCN_DECAY 106
142// New Programmable ADC Digital Path and I2C Bus Condition Register
143#define NEW_ADC_DIGITALPATH 107
144// Passive Analog Signal Bypass Selection During Powerdown Register
145#define PASSIVE_BYPASS 108
146// DAC Quiescent Current Adjustment Register
147#define DAC_ICC_ADJ 109